F439_CPP_SPI_RA8875_TFT_LCD_04 1.0
STM32F439 SPI RA8875 7-inch TFT display with FRAM-backed touch calibration, built on the STM32_GFX, STM32_RA8875 and STM32_MB85RS64V libraries
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MB85RS64V Class Reference

Driver for one MB85RS64V SPI FRAM (8192 bytes) on an STM32 HAL SPI bus. More...

#include <MB85RS64V.hpp>

Public Types

enum class  BlockProtect : uint8_t { None = 0 , UpperQuarter = STATUS_BP0 , UpperHalf = STATUS_BP1 , All = STATUS_BP1 | STATUS_BP0 }
 Areas of the array that the block-protect bits can lock against writes. More...
 

Public Member Functions

 MB85RS64V (SPI_HandleTypeDef *hspi, GPIO_TypeDef *csPort, uint16_t csPin, uint32_t timeoutMs=100, uint8_t maxAttempts=3)
 Creates the driver object; does not touch the hardware (call begin() for that).
 
bool begin ()
 Checks the SPI setup and the chip's identity, and leaves writes disabled.
 
bool readId (uint8_t *id)
 Reads the four-byte device ID (RDID, 9Fh).
 
bool read (uint16_t address, uint8_t *buffer, size_t length)
 Reads bytes from the FRAM array (READ, 03h).
 
bool write (uint16_t address, const uint8_t *data, size_t length)
 Writes bytes to the FRAM array (WREN, then WRITE, 02h); a retry repeats both steps.
 
bool writeEnable ()
 Sets the write enable latch (WREN, 06h). Normally not needed; write() does it.
 
bool writeDisable ()
 Clears the write enable latch (WRDI, 04h).
 
bool readStatus (uint8_t *status)
 Reads the status register (RDSR, 05h).
 
bool writeStatus (uint8_t status)
 Writes the status register (WREN, then WRSR, 01h); a retry repeats both steps.
 
bool setBlockProtect (BlockProtect area)
 Sets which part of the array the block-protect bits lock against writes, keeping the other writable status bits as they are.
 
HAL_StatusTypeDef lastStatus () const
 HAL status of the most recent failed SPI call (HAL_OK if none has failed). Because a failed command is retried and then ends in Error_Handler(), this is mainly useful from a custom Error_Handler() or a debugger.
 

Static Public Attributes

static constexpr uint16_t SIZE_BYTES = 8192
 Capacity in bytes (8192; addresses 0x0000 to 0x1FFF).
 
static constexpr size_t ID_LENGTH = 4
 Number of bytes returned by readId().
 
Status register bits
static constexpr uint8_t STATUS_WEL = 0x02
 Write enable latch (read-only through WRSR).
 
static constexpr uint8_t STATUS_BP0 = 0x04
 Block protect bit 0.
 
static constexpr uint8_t STATUS_BP1 = 0x08
 Block protect bit 1.
 
static constexpr uint8_t STATUS_WPEN = 0x80
 Status register write protect enable.
 

Detailed Description

Driver for one MB85RS64V SPI FRAM (8192 bytes) on an STM32 HAL SPI bus.

FRAM writes at bus speed: there is no page buffer, no erase and no write delay, so every call below completes when its SPI transfer completes. Write endurance is 10^12 cycles per byte.

Error handling
A failed HAL SPI transmit or receive is something the program cannot continue from, but only some failures are worth retrying. A transient communication failure (HAL_BUSY, HAL_TIMEOUT, or HAL_ERROR with an SPI error code for a transfer problem: mode fault, overrun, CRC, frame error, DMA or flag error) is retried: chip-select is released and the complete command is sent again, up to maxAttempts times in all. Any other failure, such as HAL_ERROR from a bad parameter or a peripheral in the wrong state, cannot be fixed by trying again and is not retried. Once the attempts are used up, or at once for a failure that is not retried, the driver calls Error_Handler() from main.h, which does not return. lastStatus() holds the HAL status of the most recent failed attempt. The methods still return false for a bad argument, and begin() returns false when the chip answers with the wrong ID or the SPI handle is configured wrongly; the caller decides what to do about those (a bridge function normally reports the reason and calls Error_Handler()).
Wiring
VCC, GND, SCK, MISO, MOSI and CS go to the MCU. The chip's HOLD input is active low and must be tied high (a low level pauses the chip and it will not answer). WP is active low and only protects the status register; tie it high so the status register stays writable. The datasheet's high input level is 0.8 x VDD, so supply the chip from the same voltage as the MCU's logic (3.3 V on a Nucleo).
Shared SPI bus
The class does not configure the SPI peripheral; CubeMX's MX_SPIx_Init() does. The chip needs master mode, 8-bit frames, MSB first, mode 0 (CPOL low, CPHA 1 edge) or mode 3 (CPOL high, CPHA 2 edge), software NSS, and a clock of 20 MHz or less; begin() checks all but the clock. It can share a bus with other SPI devices as long as each device has its own chip-select, every other device's chip-select is high while this driver talks, and the bus settings are left as above. Set the chip-select pin's initial level to high in CubeMX so the chip is deselected from reset on.
Note
Each method is documented with its definition in MB85RS64V.cpp.
Warning
Not thread-safe and not ISR-safe. Each operation asserts chip-select, makes one or more blocking HAL_SPI_Transmit()/ HAL_SPI_Receive() calls, then deasserts chip-select, with no locking in between; write() also sends a separate write-enable command first. A second caller (another RTOS task or an interrupt) that used this object, or this SPI handle, between those steps would interleave its bytes into the first caller's transaction and corrupt it. Use the object from one context only, or wrap each call in a mutex or critical section. Calls block for the length of the SPI transfer (a few milliseconds at most for 8 KB at 2 MHz).

Definition at line 78 of file MB85RS64V.hpp.

Member Enumeration Documentation

◆ BlockProtect

enum class MB85RS64V::BlockProtect : uint8_t
strong

Areas of the array that the block-protect bits can lock against writes.

Enumerator
None 

No protection.

UpperQuarter 

0x1800 to 0x1FFF protected.

UpperHalf 

0x1000 to 0x1FFF protected.

All 

0x0000 to 0x1FFF protected.

Definition at line 95 of file MB85RS64V.hpp.

Constructor & Destructor Documentation

◆ MB85RS64V()

MB85RS64V::MB85RS64V ( SPI_HandleTypeDef * hspi,
GPIO_TypeDef * csPort,
uint16_t csPin,
uint32_t timeoutMs = 100,
uint8_t maxAttempts = 3 )

Creates the driver object; does not touch the hardware (call begin() for that).

Parameters
hspiSPI handle already initialised by CubeMX.
csPortGPIO port of the chip-select pin.
csPinGPIO pin of the chip-select pin.
timeoutMsTimeout of each HAL SPI call, in milliseconds.
maxAttemptsTries per command when it fails with a transient communication error, before Error_Handler() is called; 0 is treated as 1.

Construct the object after MX_SPIx_Init() has run (for example with new inside an init function), not as a global, which would be constructed before the peripheral is configured.

Definition at line 25 of file MB85RS64V.cpp.

Member Function Documentation

◆ begin()

bool MB85RS64V::begin ( )

Checks the SPI setup and the chip's identity, and leaves writes disabled.

Returns
true if the SPI handle is set up as the chip requires and the ID reads 04h 7Fh 03h 02h (Fujitsu, 64 Kbit); false otherwise. A wrong ID usually means a wiring fault (HOLD low, wrong CS pin, no power) or a different chip. A failed transfer is handled as the class documentation describes.

Definition at line 145 of file MB85RS64V.cpp.

References ID_LENGTH, readId(), and writeDisable().

Referenced by initFRAM().

◆ lastStatus()

HAL_StatusTypeDef MB85RS64V::lastStatus ( ) const
inline

HAL status of the most recent failed SPI call (HAL_OK if none has failed). Because a failed command is retried and then ends in Error_Handler(), this is mainly useful from a custom Error_Handler() or a debugger.

Returns
The stored HAL status code.

Definition at line 129 of file MB85RS64V.hpp.

Referenced by initFRAM(), and testFRAM().

◆ read()

bool MB85RS64V::read ( uint16_t address,
uint8_t * buffer,
size_t length )

Reads bytes from the FRAM array (READ, 03h).

Parameters
addressFirst address, 0x0000 to 0x1FFF.
bufferDestination buffer of at least length bytes.
lengthNumber of bytes; address + length must not exceed SIZE_BYTES.
Returns
true on success; false for a null buffer, a zero length or a range outside the array.

Definition at line 186 of file MB85RS64V.cpp.

References SIZE_BYTES.

Referenced by testFRAM(), touchCalibrationLoad(), and touchCalibrationSave().

◆ readId()

bool MB85RS64V::readId ( uint8_t * id)

Reads the four-byte device ID (RDID, 9Fh).

Parameters
idBuffer of at least ID_LENGTH bytes. Expected: 04h (Fujitsu manufacturer), 7Fh (continuation code), 03h (64 Kbit density), 02h.
Returns
true on success; false if id is null.

Definition at line 166 of file MB85RS64V.cpp.

References ID_LENGTH.

Referenced by begin(), and initFRAM().

◆ readStatus()

bool MB85RS64V::readStatus ( uint8_t * status)

Reads the status register (RDSR, 05h).

Parameters
statusReceives the register value (see the STATUS_* constants).
Returns
true on success; false if status is null.

Definition at line 252 of file MB85RS64V.cpp.

Referenced by initFRAM(), and setBlockProtect().

◆ setBlockProtect()

bool MB85RS64V::setBlockProtect ( BlockProtect area)

Sets which part of the array the block-protect bits lock against writes, keeping the other writable status bits as they are.

Parameters
areaWhich part of the array to lock.
Returns
true on success; false if the status register could not be read first.

Definition at line 294 of file MB85RS64V.cpp.

References readStatus(), STATUS_BP0, STATUS_BP1, and writeStatus().

◆ write()

bool MB85RS64V::write ( uint16_t address,
const uint8_t * data,
size_t length )

Writes bytes to the FRAM array (WREN, then WRITE, 02h); a retry repeats both steps.

Parameters
addressFirst address, 0x0000 to 0x1FFF.
dataSource buffer of at least length bytes.
lengthNumber of bytes; address + length must not exceed SIZE_BYTES.
Returns
true on success; false for a null buffer, a zero length or a range outside the array.

The write enable latch is set before each write and clears automatically afterwards, so every call is independent. Writing into a block that setBlockProtect() has locked is silently ignored by the chip; read the data back if you need to be sure.

Definition at line 210 of file MB85RS64V.cpp.

References SIZE_BYTES.

Referenced by testFRAM(), and touchCalibrationSave().

◆ writeDisable()

bool MB85RS64V::writeDisable ( )

Clears the write enable latch (WRDI, 04h).

Returns
true on success.

Definition at line 243 of file MB85RS64V.cpp.

Referenced by begin().

◆ writeEnable()

bool MB85RS64V::writeEnable ( )

Sets the write enable latch (WREN, 06h). Normally not needed; write() does it.

Returns
true on success.

Definition at line 235 of file MB85RS64V.cpp.

◆ writeStatus()

bool MB85RS64V::writeStatus ( uint8_t status)

Writes the status register (WREN, then WRSR, 01h); a retry repeats both steps.

Parameters
statusNew value; the chip stores only WPEN, BP1 and BP0.
Returns
true on success.
Warning
With WP low and WPEN set the chip ignores this write.

Definition at line 271 of file MB85RS64V.cpp.

Referenced by setBlockProtect().

Member Data Documentation

◆ ID_LENGTH

constexpr size_t MB85RS64V::ID_LENGTH = 4
staticconstexpr

Number of bytes returned by readId().

Definition at line 84 of file MB85RS64V.hpp.

Referenced by begin(), initFRAM(), and readId().

◆ SIZE_BYTES

constexpr uint16_t MB85RS64V::SIZE_BYTES = 8192
staticconstexpr

Capacity in bytes (8192; addresses 0x0000 to 0x1FFF).

Definition at line 81 of file MB85RS64V.hpp.

Referenced by read(), touchCalibrationAttachStorage(), and write().

◆ STATUS_BP0

constexpr uint8_t MB85RS64V::STATUS_BP0 = 0x04
staticconstexpr

Block protect bit 0.

Definition at line 89 of file MB85RS64V.hpp.

Referenced by setBlockProtect().

◆ STATUS_BP1

constexpr uint8_t MB85RS64V::STATUS_BP1 = 0x08
staticconstexpr

Block protect bit 1.

Definition at line 90 of file MB85RS64V.hpp.

Referenced by setBlockProtect().

◆ STATUS_WEL

constexpr uint8_t MB85RS64V::STATUS_WEL = 0x02
staticconstexpr

Write enable latch (read-only through WRSR).

Definition at line 88 of file MB85RS64V.hpp.

◆ STATUS_WPEN

constexpr uint8_t MB85RS64V::STATUS_WPEN = 0x80
staticconstexpr

Status register write protect enable.

Definition at line 91 of file MB85RS64V.hpp.


The documentation for this class was generated from the following files: