SRAM Architecture Overview

This page describes the high-level documentation architecture for the external SRAM subsystem used by the STM32 Nucleo-H753 AS6C4008 FMC daughterboard project.

The SRAM subsystem documentation is intentionally organized into focused subgroup areas so that raw memory validation, linker/startup integration, memory-map notes, and H753-specific porting behavior can be documented separately while still remaining part of one coherent subsystem.

Architecture Navigation

Use the links below to jump directly into the subsystem-level documentation:

• SRAM Subsystem
• SRAM Validation Layer
• SRAM Integration Layer
• H753 Porting Layer
• Memory Map and Linker Layer

Documentation Flow

The documentation is intended to be read in this order:

• Project Main Page
• SRAM Architecture Overview
• External SRAM Documentation Index
• SRAM Validation Tests
• SRAM Integration Flow
• H753 Porting Notes
• H753 Memory Map and Linker Notes

Hardware Summary

This project uses a single AS6C4008 asynchronous SRAM device connected to the FMC external memory interface.

Key characteristics:

• Physical SRAM capacity: 512 KB
• FMC base address: 0x60000000
• Memory bus width: 8 bits
• SRAM integration section: .sramdata

On STM32H753, the FMC SRAM window is additionally protected with an MPU region configured to 512 KB so that the MPU footprint matches the physical capacity of the AS6C4008 device.