H753_CPP_AS6C4008_FMC_DaughterBoard_02 Documentation

This documentation covers the external SRAM bring-up, validation, linker/startup integration, and H753-specific porting work for the STM32 Nucleo-H753 AS6C4008 FMC daughterboard project.

Project Overview

The firmware targets an STM32H753 Nucleo board and also to the STM32F439 Nucleo board connected to an external Alliance Memory AS6C4008 SRAM over the FMC asynchronous memory bus. There are a less changes that must be done to support the STM32F439 board and you can refer to the documentation for the F439_CPP_AS6C4008_FMC_DaughterBoard_01 project.

This project started from a working STM32F439 reference design, but it is intentionally documented as its own project because the STM32H753 port added a distinct system-level requirement: the external SRAM window at 0x60000000 must be configured with H7-safe MPU attributes before the structured SRAM tests behave correctly.

The current project work focuses on:

• external SRAM electrical validation
• initialized-data placement into external SRAM
• startup copy from FLASH to SRAM
• structured SRAM integration testing
• retained byte-dump diagnostics for regression analysis
• H753-specific MPU requirements for external asynchronous SRAM

Project-Level Documentation

• SRAM Architecture Overview
• SRAM Subsystem Groups
• SRAM Validation Layer
• SRAM Integration Layer
• H753 Porting Layer
• Memory Map and Linker Layer
• External SRAM Documentation Index
• SRAM Validation Tests
• SRAM Integration Flow
• H753 Porting Notes
• H753 Memory Map and Linker Notes

Architectural Direction

The documentation structure is intentionally subsystem-oriented rather than a single monolithic page. This mirrors the STM32F439 project layout while still preserving the distinct identity of the H753 project and the lessons learned during the H7 porting investigation.