Overview

This project began as a port of the working STM32F439 AS6C4008 FMC daughterboard design to the STM32H753 Nucleo platform.

The board-level electrical model remained largely reusable, but the H753 required one important system-level change before structured external SRAM accesses behaved correctly: the FMC SRAM window had to be configured through the MPU as non-cacheable, non-bufferable, and shareable.

Key Porting Findings

The daughterboard wiring remained valid after the H753 FMC pin mapping was aligned with the board.
Raw SRAM validation and startup-copy behavior were not sufficient to prove full H753 correctness.
Structured field updates exposed that the Cortex-M7 memory system could interact badly with the external asynchronous SRAM window when the region was left with default memory attributes.
The retained phased byte-dump diagnostics made this visible by showing writes affecting bytes outside the intended field boundaries.

Required H753 Design Rule

The external SRAM window at 0x60000000 must be configured in main.c through MPU_Config() before HAL_Init() runs.

The required attributes are:

non-cacheable
non-bufferable
shareable
execute-never

MPU Region Size

The MPU region size is configured as:

MPU_REGION_SIZE_512KB

This matches the physical capacity of the AS6C4008 SRAM device.

A larger MPU region, such as 1 MB, can still function if the base address is aligned correctly, but it needlessly covers address space beyond the actual SRAM footprint. Using 512 KB keeps the H753 MPU configuration aligned with the physical device size and with the validated project memory map.

Failure Signature Before MPU Fix

Before the MPU region was configured correctly, the H753 project showed:

corruption of structured data fields
string and float writes affecting adjacent fields
non-deterministic integration failures even though basic access sometimes appeared plausible

Validation Result

With the MPU correctly configured:

SRAM integration tests PASS
SramValidation_RunAll() PASS
full-range pattern tests PASS across the entire 512 KB device
no corruption is observed across the validated SRAM range

Conclusion

External FMC SRAM on Cortex-M7 requires explicit MPU configuration. This requirement does not exist on STM32F4 and is the primary architectural difference between the F439 and H753 implementations in this project family.